Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening - Télécom Paris Access content directly
Conference Papers Year : 2013
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hal-02286728 , version 1 (13-09-2019)

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  • HAL Id : hal-02286728 , version 1

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Samuel Nascimento Pagliarini, Lirida Naviner, Jean-François Naviner. Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening. Journées Nationales du Réseau Doctoral de Microélectronique, Jun 2013, Grenoble, France. ⟨hal-02286728⟩
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