In this paper we present a few potentially efficient tiling patterns for gate-array realizations. We start with a brief recapitulation of tiling patterns, and fundamental limits of placement/routing in a two-dimensional plane. We state the first principles (i.e. Rent's Rule, Donath's result, equivalence of wire flux and wire length) and we proceed to define a method to mathematically evaluate tiling patterns basedon these principles. With this method we analyze a few regular tiling patterns and present a layout scheme for hexagonal and octagonal FPGAs. We briefly discuss the hierarchical gate array and we conclude with emphasis on the necessity of evolution of tiling patterns with the technology.