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Poster De Conférence Année : 2008

Efficient tiling patterns for reconfigurable gate arrays

Résumé

In this paper we present a few potentially efficient tiling patterns for gate-array realizations. We start with a brief recapitulation of tiling patterns, and fundamental limits of placement/routing in a two-dimensional plane. We state the first principles (i.e. Rent's Rule, Donath's result, equivalence of wire flux and wire length) and we proceed to define a method to mathematically evaluate tiling patterns basedon these principles. With this method we analyze a few regular tiling patterns and present a layout scheme for hexagonal and octagonal FPGAs. We briefly discuss the hierarchical gate array and we conclude with emphasis on the necessity of evolution of tiling patterns with the technology.
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Dates et versions

hal-04510620 , version 1 (19-03-2024)

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Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger. Efficient tiling patterns for reconfigurable gate arrays. SLIP08: International Workshop on System Level Interconnect Prediction, Apr 2008, Newcastle United Kingdom, United Kingdom. ACM, pp.11-18, 2008, ⟨10.1145/1353610.1353613⟩. ⟨hal-04510620⟩
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