Formal verification of SysML models contributes to early detection of design errors early in the life cycle of systems. Incremental modeling of systems leads to the repeated verification of parts of systems models that were already verified in previous versions of the SysML model. This paper proposes to optimize the verification process by generating dependency graphs from SysML models. This revisited verification technique is now supported by TTool. It is illustrated with an Avionics Full DupleX network.