System-Theoretic Process Analysis (STPA) is a technique , based on System-Theoretic Accident Model and Process (STAMP), to identify hazardous control actions, loss scenarios, and safety requirements. STPA is considered a rather complex technique and lacks formalism, but there exists a growing interest in using STPA in certifications of safety-critical systems development. SysML is a modeling language for systems engineering. It enables representing models for analysis, design, verification, and validation of systems. In particular, the free software TTool and the model-checker UPPAAL enable formal verification of SysML models. This paper proposes a method that combines STPA and SysML modeling activities in order to allow simulation and formal verification of systems' models. An automatic door system serves as example to illustrate the effectiveness of the proposed approach.