Intellectual Property (IP) reuse has become one of the keys to enabling today’s massive System-on-Chip (SoC) designs. However the extensive reuse of IP components has increased the challenge of SoC verification. The higher-level abstraction of IPs allows designers to manage this complexity in today’s multi-million gate SoC. Abstraction of complex calcu- lations in data paths greatly simplifies the design for verification. For such an abstraction we first need to separate control from data in IPs. In this paper we have presented an extension to control-data slicing paradigm [4] in which a Register Transfer Level (RTL) transformation of IP models is proposed assisting separation of control state machines from the data processing. Before slicing an IP model into control and data, we first make a transformation which preserves the model semantics. The existing slicing paradigm is enriched by additional analysis and applied to the transformed model which enables the control-data slicing of more general RTL IP models particularly VHDL models with extensive use of local variables.