Hardware Optimized Sample Rate Conversion for Software Defined Radio - Télécom Paris
Article Dans Une Revue Frequenz Journal of RF-Engineering and Telecommunications Année : 2010

Hardware Optimized Sample Rate Conversion for Software Defined Radio

Raymond Knopp
Renaud Pacalet

Résumé

The evolution towards applications with increasing functionalities leads to the need of high flexible systems that support a high number of different standards while decreasing the required hardware space. Therefore a high configurable platform being able to handle a multitude of standards is needed. One main issue is the tradeoff between performance and space consumption. We present a generic, flexible, fractional and hardware optimized SRC architecture in the context of SDR, providing one architecture to process up to 8 different complex channels. The solution is based on bandlimited interpolation and allows processing by supporting a 1Hz resolution of the sampling rates.
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Dates et versions

hal-02893096 , version 1 (08-07-2020)

Identifiants

  • HAL Id : hal-02893096 , version 1

Citer

Raymond Knopp, Carina Schmidt-Knorreck, Renaud Pacalet. Hardware Optimized Sample Rate Conversion for Software Defined Radio. Frequenz Journal of RF-Engineering and Telecommunications, 2010. ⟨hal-02893096⟩
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