In this article we present the architecture of a quaternary FPGA, its implementation in FDSOI technology, and a comparison with binary architectures based on VPR. We discuss the transistor level design of LUTs, Flip-Flops, Muxes, and multi-valued buffer circuits exploiting the capability of FDSOI technology to modify threshold voltages. We present I/O elements of such an FPGA with binary to quaternary translators and a new technique to reduce global routing by combining clock and reset on the same wire. We model the area, delay and power consumption of the quaternary FPGA architecture in VPR. We compare the implementation of very simple arithmetic benchmarks with equivalent two-valued FPGA architectures in VPR. We show that, it is possible to achieve upto 15% reduction in transistor area, and 10% reduction in critical path delay.