Test Sequence Generation From Formally Verified SysML Models - Télécom Paris
Communication Dans Un Congrès Année : 2019

Test Sequence Generation From Formally Verified SysML Models

Résumé

Test generation has been acknowledged as a cost-prone activity reducing productivity and time to market. The expected benefits of Model Based Systems Engineering include automated generation of test sequences from models. The paper proposes verification solutions for the System Modeling Language (SysML). In particular, the paper shows how to link test generation to formal verification. The proposed algorithms are implemented by the free software TTool. Two case studies support discussion on conformance and interoperability testing, respectively.
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Dates et versions

hal-02337493 , version 1 (29-10-2019)

Identifiants

  • HAL Id : hal-02337493 , version 1

Citer

Pierre de Saqui-Sannes, Ludovic Apvrille. Test Sequence Generation From Formally Verified SysML Models. Asia-Pacific Software Engineering Conference (APSEC'2019), Feb 2019, Stuttgart, Germany. ⟨hal-02337493⟩
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