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Communication Dans Un Congrès Année : 2008

An 8x8 run-time reconfigurable FPGA embedded in a SoC

Résumé

This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(Hardware Blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.

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Dates et versions

hal-04510633 , version 1 (19-03-2024)

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Citer

Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger. An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC '08: The 45th Annual Design Automation Conference 2008, Jun 2008, Anaheim California, United States. pp.120-125, ⟨10.1145/1391469.1391500⟩. ⟨hal-04510633⟩
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