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Communication Dans Un Congrès Année : 2007

Efficient Modeling and Floorplanning of Embedded-FPGA Fabric

Résumé

In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR tool, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing for island style FPGAs using rectilinear macros. Several system integration issues are highlighted. Layout of a real life SOC with an embedded RTR FPGA for cryptographic applications, designed with this flow, is also presented.
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Dates et versions

hal-04510607 , version 1 (19-03-2024)

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Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley. Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. 2007 International Conference on Field Programmable Logic and Applications, Aug 2007, Amsterdam, Netherlands. pp.665-669, ⟨10.1109/FPL.2007.4380741⟩. ⟨hal-04510607⟩
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