FPGA design of an Open-Loop True Random Number Generator - Télécom Paris Access content directly
Conference Papers Year : 2013

FPGA design of an Open-Loop True Random Number Generator

Abstract

This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4% of the available resources and generates random bits at a 20 Mbps rate. This work gives a detailed description of the design methodology, more specifically the placement, routing and timing analysis of the TRNG structure. Also, the randomness quality of this TRNG has been validated using AIS-31 and NIST statistical tests
No file

Dates and versions

hal-02412025 , version 1 (15-12-2019)

Identifiers

Cite

Florent Lozac'H, Molka Ben Romdhane, Tarik Graba, Jean-Luc Danger. FPGA design of an Open-Loop True Random Number Generator. 16th euromicro conference on digital system design, Sep 2013, Santander, Spain. pp.615-622, ⟨10.1109/DSD.2013.73⟩. ⟨hal-02412025⟩
34 View
0 Download

Altmetric

Share

Gmail Facebook X LinkedIn More