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authIdHal_s : yves-mathieu

The “Backend Duplication” Method

Sylvain Guilley , Philippe Hoogvorst , Yves Mathieu , Renaud Pacalet
Workshop on Cryptographic Hardware and Embedded Systems (CHES), Aug 2005, Edinburgh, United Kingdom. pp.383-397, ⟨10.1007/11545262_28⟩
Conference papers hal-02893271v1
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Formal Evaluation and Construction of Glitch-resistant Masked Functions

Sofiane Takarabt , Sylvain Guilley , Youssef Souissi , Khaled Karray , Laurent Sauvage et al.
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Dec 2021, Virtual, United States
Conference papers hal-03365025v1
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Cryptographically Secure Shield for Security IPs Protection

Xuan-Thuy Ngo , Jean-Luc Danger , Sylvain Guilley , Tarik Graba , Yves Mathieu et al.
IEEE Transactions on Computers, 2017, 66 (2), ⟨10.1109/TC.2016.2584041⟩
Journal articles hal-02287686v1
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Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.

Laurent Sauvage , Sylvain Guilley , Jean-Luc Danger , Yves Mathieu , Maxime Nassar et al.
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645
Conference papers hal-00325417v3
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Efficient data access management for FPGA-Based image processing SoCs

Zahir Larabi , Yves Mathieu , Stéphane Mancini
20th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP\'2009), Jun 2009, Paris, France. pp.159-165
Conference papers hal-00368532v2
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Security Evaluation of a Balanced Quasi-Delay Insensitive Library (SecLib)

Sylvain Guilley , Florent Flament , Yves Mathieu , Renaud Pacalet
Conference on Design of Circuits and Integrated Systems, Nov 2008, Grenoble, France. 6 p., ISBN: 978-2-84813-124-5
Conference papers hal-00283405v5

Calibrating a predictive cache emulator for SoC design

Stéphane Mancini , Lionel Pierrefeu , Zahir Larabi , Yves Mathieu
NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Jun 2010, Anaheim, Californie, United States. pp.273-280, ⟨10.1109/AHS.2010.5546246⟩
Conference papers hal-02278686v1

Diffusional Side-channel Leakage from Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE

Ville Yli-Mayry , Rei Ueno , Noriyuki Miura , Makoto Nagata , Shivam Bhasin et al.
IEEE Transactions on Information Forensics and Security, 2020, pp.1-1. ⟨10.1109/TIFS.2020.3033441⟩
Journal articles hal-02977542v1
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Cryptographically secure shields

Jean-Michel Cioranesco , Jean-Luc Danger , Tarik Graba , Sylvain Guilley , Yves Mathieu et al.
HOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩
Conference papers hal-01110463v1
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Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.

Laurent Sauvage , Sylvain Guilley , Jean-Luc Danger , Yves Mathieu , Maxime Nassar et al.
Preprints, Working Papers, ... hal-00339858v1
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Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs

Sylvain Guilley , Laurent Sauvage , Jean-Luc Danger , Tarik Graba , Yves Mathieu et al.
Secure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩
Conference papers hal-00259153v5

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

Jean-Luc Danger , Risa Yashiro , Tarik Graba , Yves Mathieu , Abdelmalek Si-Merabet et al.
2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.508-515
Conference papers hal-02271687v1

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology

Shivam Bhasin , Jean-Luc Danger , Tarik Graba , Yves Mathieu
ES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩
Conference papers hal-02412041v1

A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor

Noriyuki Miura , Kohei Matsuda , Karol Myszkowski , Makoto Nagata , Shivam Bhasin et al.
Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267
Conference papers hal-02288491v1

Detection of Side-channel Lleakage Through Glitches Using an Automated Tool

Laurent Sauvage , Sofiane Takarabt , Youssef Souissi , Sylvain Guilley , Yves Mathieu et al.
International Conference on Defense Systems: Architectures and Technologies (DAT’2020), Apr 2020, Constantine, Algeria
Conference papers hal-02951758v1

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology

Sumanta Chaudhuri , Tarik Graba , Yves Mathieu
Preprints, Working Papers, ... hal-02287527v1

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Emna Amouri , Shivam Bhasin , Yves Mathieu , Tarik Graba , Jean-Luc Danger et al.
FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩
Conference papers hal-01372613v1

A Dual Threshold Voltage Technique for Glitch Minimization

Mariem Slimani , Philippe Matherat , Yves Mathieu
19th IEEE International Conference on Electronics, Circuits and Systems, Dec 2012, Séville, Spain. pp.444-447, ⟨10.1109/ICECS.2012.6463554⟩
Conference papers hal-01166345v1

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors

Sylvain Guilley , Florent Flament , Philippe Hoogvorst , Renaud Pacalet , Yves Mathieu et al.
IEEE Design & Test of Computers, 2007, 24 (6), pp.546-555. ⟨10.1109/MDT.2007.202⟩
Journal articles hal-02893104v1

Mutational, functional, and expression studies of the TCF4 gene in Pitt-Hopkins syndrome

Loic de Pontual , Yves Mathieu , Christelle Golzio , Marlène Rio , Valérie Malan et al.
Human Mutation, 2009, 30 (4), pp.669-676. ⟨10.1002/humu.20935⟩
Journal articles istex hal-02134020v1
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Fault Analysis Assisted by Simulation

Kais Chibani , Adrien Facon , Sylvain Guilley , Damien Marion , Yves Mathieu et al.
Jakub Breier; Xiaolu Hou; Shivam Bhasin. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, 978-3-030-11332-2. ⟨10.1007/978-3-030-11333-9_12⟩
Book sections hal-02915671v1

23 : Graphics Composition for Multiview Displays

J. Le Feuvre , Yves Mathieu
Emerging Technologies for 3D Video, Wiley, 2013
Book sections hal-02286558v1
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High Efficiency Reconfigurable Cache for Image Processing

Zahir Larabi , Yves Mathieu , Stéphane Mancini
ERSA'2009, Jul 2009, Las Vegas USA, United States. pp.226-232
Conference papers hal-00384989v1
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Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

Shivam Bhasin , Jean-Luc Danger , Florent Flament , Tarik Graba , Sylvain Guilley et al.
ReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩
Conference papers hal-00411843v3

Design Methodology of an ASIC TRNG based on an open-loop delay chain

Molka Ben Romdhane , Jean-Luc Danger , Tarik Graba , Yves Mathieu
NEWCAS, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573654⟩
Conference papers hal-02411986v1

IC variability : Pros and cons for security blocks

Jean-Luc Danger , Yves Mathieu , Thibault Porteboeuf
TRUDEVICE, Mar 2015, Grenoble, France
Conference papers hal-02412162v1

Pre-Silicon Embedded System Evaluation as new EDA for Security Verification

Sofiane Takarabt , Kais Chibani , Youssef Souissi , Laurent Sauvage , Sylvain Guilley et al.
International Verification and Security Workshop (IVSW), Jun 2018, Platja d’Aro, Spain
Conference papers hal-02287930v1

Countering Early Propagation and Routing Imbalance of DPL

Emna Amouri , Shivam Bhasin , Yves Mathieu , Tarik Graba , Jean-Luc Danger et al.
International Conference on IC Design and Technology (ICICDT), Jun 2015, Leuven, Belgium. ⟨10.1109/ICICDT.2015.7165897⟩
Conference papers hal-02287122v1