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authFullName_s : Shivam Bhasin

NICV: Normalized Inter-Class Variance for Detection of Side-Channel Leakage

Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Zakaria Najm
EMC, May 2014, Tokyo, Japan
Conference papers hal-02412040v1
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Cryptographically Secure Shield for Security IPs Protection

Xuan-Thuy Ngo , Jean-Luc Danger , Sylvain Guilley , Tarik Graba , Yves Mathieu et al.
IEEE Transactions on Computers, 2017, 66 (2), ⟨10.1109/TC.2016.2584041⟩
Journal articles hal-02287686v1

Analysis and Improvements of the DPA Contest v4 Implementation

Shivam Bhasin , Nicolas Bruneau , Jean-Luc Danger , Sylvain Guilley , Zakaria Najm et al.
SPACE, Oct 2014, Pune, India. ⟨10.1007/978-3-319-12060-7_14⟩
Conference papers hal-02288411v1

Exploiting FPGA Block Memories for Protected Cryptographic Implementations

Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Wei He
Journal articles hal-02287502v1

From cryptography to hardware: analyzing embedded Xilinx BRAM for cryptographic applications

Shivam Bhasin , Sylvain Guilley , Jean-Luc Danger
HASP, Dec 2012, Vancouver, Canada. ⟨10.1109/MICROW.2012.11⟩
Conference papers hal-02411933v1

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA

Debapriya Basu Roy , Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Wei He et al.
Journal of Hardware and Systems Security, 2018, ⟨10.1007/s41635-018-0035-4⟩
Journal articles hal-02288011v1

Diffusional Side-channel Leakage from Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE

Ville Yli-Mayry , Rei Ueno , Noriyuki Miura , Makoto Nagata , Shivam Bhasin et al.
IEEE Transactions on Information Forensics and Security, 2020, pp.1-1. ⟨10.1109/TIFS.2020.3033441⟩
Journal articles hal-02977542v1

A Look into SIMON from a Side-channel Perspective

Shivam Bhasin , Tarik Graba , Jean-Luc Danger , Zakaria Najm
HOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855568⟩
Conference papers hal-02412115v1

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage

Daisuke Fujimoto , Noriyuki Miura , Makoto Nagata , Yuichi Hayashi , Naofumi Homma et al.
IEICE Transactions on Electronics, 2014, E97.C (4), pp. 272-279
Journal articles hal-01540373v1

Towards Different Flavors of Combined Side Channel Attacks

Youssef Souissi , Shivam Bhasin , Maxime Nassar , Sylvain Guilley , Jean-Luc Danger et al.
CT-RSA, Feb 2012, San Francisco, United States. pp.245-259, ⟨10.1007/978-3-642-27954-6_16⟩
Conference papers hal-02288312v1

Side-channel leakage on silicon substrate of CMOS cryptographic chip

Daisuke Fujimoto , Daichi Tanaka , Noriyuki Miura , Makoto Nagata , Yu-Ichi Hayashi et al.
HOST, May 2014, Washington DC, United States. ⟨10.1109/HST.2014.6855564⟩
Conference papers hal-02412069v1
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Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses

Xuan Thuy Ngo , Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Zakaria Najm et al.
IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2015, May 2015, McLean, United States. ⟨10.1109/HST.2015.7140242⟩
Conference papers hal-01240228v1

Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks

N. Selmane , Shivam Bhasin , Sylvain Guilley , Jean-Luc Danger
Information Security, IET, 2011, 5 (4), pp.181-190. ⟨10.1049/iet-ifs.2010.0238⟩
Journal articles hal-02286262v1
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Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the Evaluator

Sylvain Guilley , Olivier Meynard , Maxime Nassar , Guillaume Duc , Philippe Hoogvorst et al.
Design & Technology of Integrated Systems, Apr 2011, Athens, Greece. pp.6, ⟨10.1109/DTIS.2011.5941419⟩
Conference papers hal-00579020v2
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Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors

Jean-Luc Danger , Sylvain Guilley , Shivam Bhasin , Maxime Nassar , Laurent Sauvage et al.
Preprints, Working Papers, ... hal-00431261v1
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The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations

Stjepan Picek , Annelie Heuser , Alan Jovic , Shivam Bhasin , Francesco Regazzoni et al.
IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019, 2019 (1), pp.1-29. ⟨10.13154/tches.v2019.i1.209-237⟩
Journal articles hal-01935318v1
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Hardware Trojan Horses in Cryptographic IP Cores

Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Xuan Thuy Ngo , Laurent Sauvage et al.
FDTC (Fault Detection and Tolerance in Cryptography), Aug 2013, Santa Barbara, United States. pp.15-29, ⟨10.1109/FDTC.2013.15⟩
Conference papers hal-00855146v2
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Challenges in Designing Trustworthy Cryptographic Co-Processors

Ricardo Chaves , Giorgio Di Natale , Lejla Batina , Shivam Bhasin , Baris Ege et al.
ISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. pp.2009-2012, ⟨10.1109/ISCAS.2015.7169070⟩
Conference papers lirmm-01234083v1


Makoto Nagata , Daisuke Fujimoto , Jean-Luc Danger , Shivam Bhasin
Japan, Patent n° : JP20150004346 20150113. MN:OCM. 2015
Patents hal-02412551v1
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Time-frequency analysis for second-order attacks

Pierre Belgarric , Shivam Bhasin , Nicolas Bruneau , Jean-Luc Danger , Nicolas Debande et al.
Smart Card Research and Advanced Application Conference (CARDIS 2013), Nov 2013, Berlin, Germany. pp.108-122, ⟨10.1007/978-3-319-08302-5_8⟩
Conference papers hal-02299996v1

From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications

Sylvain Guilley , Shivam Bhasin , Annelie Heuser , Jean-Luc Danger
Journal articles hal-02286503v1

Theory of masking with codewords in hardware: low-weight $d$th-order correlation-immune Boolean functions

Shivam Bhasin , Claude Carlet , Sylvain Guilley
IACR eprint archive, 2013
Journal articles hal-02286840v1

Side-channel leakage and trace compression using normalized inter-class variance.

Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Zakaria Najm
HASP, Jun 2014, Minneapolis, United States. ⟨10.1145/2611765.2611772⟩
Conference papers hal-02412117v1

Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology

Shivam Bhasin , Jean-Luc Danger , Tarik Graba , Yves Mathieu
ES4CPS, Mar 2014, Dresden, Germany. ⟨10.1145/2559627.2559628⟩
Conference papers hal-02412041v1

A Low-Entropy First-Degree Secure Provable Masking Scheme for Resource-Constrained Devices

Shivam Bhasin , Jean-Luc Danger , Sylvain Guilley , Zakaria Najm
WESS, Sep 2013, Montreal, Canada. ⟨10.1145/2527317.2527324⟩
Conference papers hal-02412039v1

A 2.5ns-Latency 0.39pJ/b 289µm2/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor

Noriyuki Miura , Kohei Matsuda , Karol Myszkowski , Makoto Nagata , Shivam Bhasin et al.
Symposium on VLSI Circuits, Jun 2017, Kyoto, Japan. pp.C266-C267
Conference papers hal-02288491v1

PLL to the rescue: a novel EM fault countermeasure

Noriyuki Miura , Zakaria Najm , Wei He , Shivam Bhasin , Xuan-Thuy Ngo et al.
DAC, Jun 2016, Austin, United States. ⟨10.1145/2897937.2898065⟩
Conference papers hal-02288461v1

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security

Emna Amouri , Shivam Bhasin , Yves Mathieu , Tarik Graba , Jean-Luc Danger et al.
FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩
Conference papers hal-01372613v1
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Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks

Shivam Bhasin , Sylvain Guilley , Laurent Sauvage , Jean-Luc Danger
Josef Pieprzyk. Topics in Cryptology - CT-RSA 2010. The 10th Cryptographers' Track at the RSA Conference 2010, San Francisco, CA, USA, March 1-5, 2010. Proceedings, 5985, Springer Berlin Heidelberg, pp.195-207, 2010, Lecture Notes in Computer Science, 978-3-642-11924-8. ⟨10.1007/978-3-642-11925-5_14⟩
Book sections hal-03766332v1
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Integrated Sensor: A Backdoor for Hardware Trojan Insertions?

Xuan Thuy Ngo , Zakaria Najm , Shivam Bhasin , Debapriya Basu , Jean-Luc Danger et al.
Euromicro Conference on Digital System Design (DSD) 2015, Aug 2015, Funchal, Portugal. ⟨10.1109/DSD.2015.119⟩
Conference papers hal-01240221v1