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Communication Dans Un Congrès Année : 2004

CMOS structures suitable for secured hardware

Résumé

Unsecured electronic circuits leak physical syndromes correlated to the data they handle. Side-channels attacks, like SPA or DPA, exploit this information leakage. We provide balanced and memoryless CMOS structures for a 2-input secured NAND gate.
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Dates et versions

hal-02893279 , version 1 (08-07-2020)

Identifiants

Citer

S. Guilley, P. Hoogvorst, Y. Mathieu, Renaud Pacalet, J. Provost. CMOS structures suitable for secured hardware. Design, Automation and Test in Europe Conference and Exhibition, Feb 2004, Paris, France. pp.1414-1415, ⟨10.1109/DATE.2004.1269113⟩. ⟨hal-02893279⟩
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